It seems these features will be available throughout the Zen 6 line and configurable via BIOS/UEFI.

From the AMD Zen 6 PQOS Extensions Whitepaper:

GLBE provides a mechanism for software to specify bandwidth limits for groups of logical processors that span multiple QOS Domains. This collection of QOS Domains is referred to as the GLBE Control Domain. The GLBE Ceiling is a bandwidth ceiling for L3 External Bandwidth competitively shared between all logical processors in a given Class of Service (COS) across all QOS Domains within the GLBE Control Domain.

By default, all QOS Domains in the system are included in a single GLBE Control Domain. However, BIOS
options may establish several GLBE Control Domains within the system.

I am assuming you will need motherboard support and OEMs will limit this to expensive enterprise SKU. Much like ECC and anything beyond dual channel memory.

That being said, I can’t really think of any mainstream uses cases where this would be helpful. The only thing that comes to mind is a homelab / DIY workstation case where you have a powerful CPU that you run background tasks on while using it for mid to low level work cases while those background tasks are running. And even then this would depend on how the sensitivity of your task to L3 cache availability.

I do a lot of video encoding/ML Upscaling (sometimes a 10 minute 1080p video can take around 5-6 hours to upscale to 4K using extremely aggressive settings that heavily prioritize output quality relative to processing demand) and even with some limits on GPU/CPU throughput, I can’t fully make the background task not interfere with whatever I am doing if I am upscaling to 4K).